MP7613

7

Rev. 2.00

Data

Input/Output

Bus

Address

A0-A2

Chip Select

CS

Load Latch A

LD1

Load Latch B

LD2

1

0

1

0

1

0

1

0

1

0

+FS

–FS

Analog Output

don’t care

don’t care

Notes

(1)

Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable

in the above diagram.

(2)

R1 = R2 = 1.

(3)

For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).

Address

A0-A2

Chip Select

CS

Data Readback

RD

Digital Output Data

D0 to D13

don’t care

don’t care

HIGH-Z

HIGH-Z

1

0

1

0

1

0

1

0

Notes

(1)

Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable

in the above diagram.

(2)

R1 = R2 = 1.

R1

R2

Reset first latch bank to

1000 . . . . .0000

Reset second latch bank to 1000 . . . . .0000 and analog

output to zero volt.

1

0

1

0

Figure 1. Loading Latch A and Updating Latch B

Figure 2. Read Back First Latch Bank of One DAC

Figure 3. Reset Operations