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SC14CVMDECT-SF Folha de dados(PDF) 32 Page - Dialog Semiconductor |
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SC14CVMDECT-SF Folha de dados(HTML) 32 Page - Dialog Semiconductor |
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32 / 57 page ![]() Datasheet Revision 3.0 28-Jul-2015 CFR0011-120-00-FM Rev 5 32 of 57 © 2013 Dialog Semiconductor SC14CVMDECT SF Cordless Voice Module FINAL 5-4 R/W P0_3_MODE 00 = P0_OUT_DATA_REG[3] on P0[3] 01 = SCL2 on P0[3] (Note 14) 1x = Reserved 0 3-2 R/W P0_2_MODE 00 = P0_OUT_DATA_REG[2] on P0[2] 01 = SDA2 on P0[2] (Note 14) 10 = UART UTX2 on P0[2] 1x = Reserved 0 1 R/W P0_1_MODE 0 = P0_OUT_DATA_REG[1] on P0[1] 1 = Timer 0 PWM0 on P0[1] 0 0 R/W P0_0_MODE 0 = P0_OUT_DATA_REG[0] on P0[0] 1 = UART UTX on P0[0] 0 NOTE: This register is not reset with a SW reset Table 13: P1_MODE_REG (0xFF4848) Bit Mode Symbol Description Reset 15-10 - 0 9-8 R/W RF_BB_MODE 00 01 10 P1[5] See P1_5_MODE RDI output RDI input P1[4] See P1_4_MODE TDOD output TDOD output P1[3] See P1_3_MODE SIO output SIO input/output P1[2] See P1_2_MODE SK output SK output P1[1] See P1_1_MODE LE output LE output 0 7-5 - P1_5_MODE Reserved 0 4 R/W P1_4_MODE 0 = P1_OUT_DATA_REG[4] on P1[4] (2 mA drive) 1 = P1_OUT_DATA_REG[4] on P1[4] (1 mA drive) for direct connec- tion to base of external NPN transistor. 0 3 R/W P1_3_MODE 0 = P1_OUT_DATA_REG[3] on P1[3] (2 mA drive) 1 = P1_OUT_DATA_REG[3] on P1[3] (1 mA drive) for direct connec- tion to base of external NPN transistor. 0 2 - P1_2_MODE Reserved 0 1 - P1_1_MODE Reserved 0 0 R/W P1_0_MODE 0 = P1_OUT_DATA_REG[0] on P1[0] ADC1 input disabled, input up-to VDD+0.3 V 1 = Analog ADC1 mode, input up to 1.98 V!! P1_DIR_REG[0] must be set to 0, to disable Pull-up, pull-down and digital output mode. 1 NOTE: This register is not reset with a SW reset Table 14: P2_MODE_REG (0xFF4858) BIT MODE SYMBOL DESCRIPTION RESET 15 R/W P2_7_MODE 0 = P2_OUT_DATA_REG[7] on P2[7] 1 = BXTAL on P2[7] (Can be used as RFCLK for external RF) 0 14 R/W INT7_MODE 0 = P2[7] input to INT7 1 = P1[2] input to INT7 0 13 R/W P2_6_MODE 0 = P2_OUT_DATA_REG[6] on P2[6] 1 = WTF_IN on P2[6] (monitor Gen2DSP load) 0 12 R/W INT6_MODE 0 = P2[6] to INT6 1 = P1[1] to INT6 0 Table 12: P0_MODE_REG (0xFF4838) Bit Mode Symbol Description Reset |
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