STV3550 datasheet(81/144 Pages) STMICROELECTRONICS

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CPU and System Management Functional Description

STV3550

81/144

6.3.12 STV3550 External and Internal Memory Mapping

The internal and external memory maps in the STV3550 is described in Figure 52.

6.4

Reset Strategy

The chip includes 3 different types of reset:

1. An external Hard Reset controlled by the NRESET pin and usually used for the Power On

Reset (POR)

2. An internal reset generated by the Watchdog

3. A Soft Reset controlled by the ST20 C2C200 CPU core

6.4.1

External Hard Reset

Figure 52: Internal and External Memory Map

Figure 53: External Hard Reset

STV3550

Address Space

Memory Resource Type

80000000

80001FFF

ST20 Internal SRAM (8 KBytes)

Other STV3550 Peripheral Registers

(Display...)

00000000

1FFFFFFF

ST20 Peripheral Registers (INTC,

DCU, Caches)

20000000

30005FFF

40000000

41FFFFFF

7FFE0000

50000000

67FFFFFF

SDRAM (up to 32 MBytes)

7FFFFFFF

Flash (up to 2 MBytes)

STV3550 Memory Interface Control Registers

7FFFFFFF

40000000

3FFFFFFF

00000000

FFFFFFFF

C0000000

BFFFFFFF

80000000

Internal

Memory

Resource

Internal

Memory

Resource

Internal

Memory

Resource

External

Memory

Resource

External

Memory

Resource

Build-Up

Counter

NRESET

Reset Pad

notRST

27-MHz

Crystal Clock

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