General Description
The ’165 is an 8-bit parallel load or serial-in register with
complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load
(PL) input is LOW. With PL HIGH, serial shifting occurs on
the rising edge of the clock; new data enters via the Serial
Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as
an active LOW clock enable.