DESCRIPTION

The 74LVC1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74LVC1G17 provides a buffer function with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined outputs.

FEATURES

• Wide supply voltage range from 1.65 V to 5.5 V

• High noise immunity

• Complies with JEDEC standard:

   – JESD8-7 (1.65 V to 1.95 V)

   – JESD8-5 (2.3 V to 2.7 V)

   – JESD8B/JESD36 (2.7 V to 3.6 V).

• ±24 mA output drive (VCC = 3.0 V)

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Unlimited rise and fall times

• Input accepts voltages up to 5 V

• ESD protection:

   – HBM EIA/JESD22-A114-B exceeds 2000 V

   – MM EIA/JESD22-A115-A exceeds 200 V.

• Multiple package options

• Specified from −40 °C to +85 °C and −40 °C to +125 °C.