GENERAL DESCRIPTION
The PCnet-ISA II controller, a single-chip Ethernet controller, is a highly integrated system solution for the PC-AT Industry Standard Architecture (ISA) architecture. It is designed to provide flexibility and compatibility with any existing PC application. This highly integrated VLSI device is specifically designed to reduce parts count and cost, and addresses applications where higher system throughput is desired. The PCnet-ISA II controller is fabricated with AMD’s advanced low-power CMOS process to provide low standby current for power sensitive applications.

DISTINCTIVE CHARACTERISTICS
■ Single-chip Ethernet controller for the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) buses
■ Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards
■ Supports full duplex operation on the 10BASE-T, AUI, and GPSI ports
■ Direct interface to the ISA or EISA bus
■ Pin compatible to Am79C961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
■ Software compatible with AMD’s Am7990 LANCE register and descriptor architecture
■ Low power, CMOS design with sleep mode allows reduced power consumption for critical battery powered applications
■ Individual 136-byte transmit and 128-byte receive FIFOs provide packet buffering for increased system latency, and support the following features:
   — Automatic retransmission with no FIFO reload
   — Automatic receive stripping and transmit padding (individually programmable)
   — Automatic runt packet rejection
   — Automatic deletion of received collision frames
■ Dynamic transmit FCS generation programmable on a frame-by-frame basis
■ Single +5 V power supply
■ Internal/external loopback capabilities
■ Supports 8K, 16K, 32K, and 64K Boot PROMs or Flash for diskless node applications
■ Supports Microsoft’s Plug and Play System configuration for jumperless designs
■ Supports staggered AT bus drive for reduced noise and ground bounce
■ Integrated Magic Packet™ support for remote wake up of Green PCs
■ Supports 8 interrupts on chip
■ Look Ahead Packet Processing (LAPP) allows protocol analysis to begin before end of receive frame
■ Supports 4 DMA channels on chip
■ Supports 16 I/O locations
■ Supports 16 boot PROM locations
■ Provides integrated Attachment Unit Interface (AUI) and 10BASE-T transceiver with 2 modes of port selection:
   — Automatic selection of AUI or 10BASE-T
   — Software selection of AUI or 10BASE-T
■ Automatic Twisted Pair receive polarity detection and automatic correction of the receive polarity
■ Supports bus-master, programmed I/O, and shared-memory architectures to fit in any PC application
■ Supports edge and level-sensitive interrupts
■ DMA Buffer Management Unit for reduced CPU intervention which allows higher throughput by by-passing the platform DMA
■ JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test
■ Integrated Manchester Encoder/Decoder
■ Supports the following types of network interfaces:
   — AUI to external 10BASE2, 10BASE5, 10BASE-T or 10BASE-F MAU
   — Internal 10BASE-T transceiver with Smart Squelch to Twisted Pair medium
■ Supports LANCE General Purpose Serial Interface (GPSI)
■ 132-pin PQFP and 144-pin TQFP packages
■ Supports Shared Memory and PIO modes
■ Supports PCMCIA mode (144-TQFP version only)
■ Support for operation in industrial temperature range (–40°C to +85°C) available in both packages