▪ Phase-Lock Loop clock distribution
▪ 10MHz to 133MHz operating frequency
▪ Distributes one clock input to one bank of five outputs
▪ Zero input-output delay
▪ Output skew < 250ps
▪ Low jitter < 200ps cycle-to-cycle
▪ 2305-1 for Standard drive
▪ 2305-1H for High drive
▪ No external RC network required
▪ Operates at 3.3V VDD
▪ Power-down mode
▪ Available in SOIC/TSSOP packages