▪ High-performance clock RF sampling clock
generator and clock jitter attenuator with support
for JESD204B/C
▪ Low phase noise: -144.7dBc/Hz (800kHz offset;
491.52MHz)
▪ Integrated phase noise of 74fs RMS (12k-20MHz,
491.52MHz)
▪ Dual-PLL architecture with internal and optional
external VCO
▪ Eight output channels with a total of 16 outputs
▪ Configurable integer clock frequency dividers
▪ Clock output frequencies: up to 3932.16MHz
(Internal VCO) and  6GHz (optional external VCO)
▪ Differential, low noise I/O
▪ Deterministic phase delay and integrated phase
delay circuits
▪ Redundant input clock architecture with two inputs
and monitors, holdover, and input switching
▪ SPI 3/4 wire configuration interface
▪ Supply voltage: 1.8V, 2.5V, and 3.3V
▪ Package: 76 VFQFN (9 x 9 mm²)
▪ Temperature range: -40°C to +105°C (board)