120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark,
up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM,
various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit, 12-bit A/D converter, RTC, Encryption function, Serial sound interface, Remote control signal receiver

■ 32-bit RXv3 CPU core
 Maximum operating frequency: 120 MHz
Capable of 707 CoreMark in operation at 120 MHz
 Double-precision 64-bit IEEE-754 floating point
 A collective register bank save function is available.
 Supports the memory protection unit (MPU)
 JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
 Operation from a single 2.7- to 3.6-V supply
 Battery supply of backup power allows continued operations of the
RTC and the backup registers.
 Four low-power modes
■ On-chip code flash memory
 Supports versions with up to 2 Mbytes of ROM
 No wait cycles at up to 60 MHz or when the ROM cache is hit, onewait
state at up to 120 MHz
 User code is programmable by on-board or off-board programming.
 Programming/erasing as background operations (BGOs)
 A dual-bank structure allows exchanging the start-up bank.
■ On-chip data flash memory
 8 Kbytes, reprogrammable up to 100,000 times
 Programming/erasing as background operations (BGOs)
■ On-chip SRAM
 384 Kbytes of SRAM (no wait states)
 4 Kbytes of standby RAM (backup on deep software standby)