▪ Distribution, fanout, phase-delay of clock and SYSREF signals
▪ Very low output noise floor: -158.8dBc/Hz noise floor
(245.76MHz)
▪ Supports clock frequencies up to 3GHz, including clock output
frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and
122.88MHz
▪ Four output channels with a total of 16 differential outputs
▪ Each channel contains frequency dividers and clock phase delay
circuits
▪ Phase alignment mode across multiple buffers with any frequency
divider setting
▪ Flexible differential outputs (LVDS/LVPECL/amplitude
configurable)
▪ Configuration through 3-wire SPI interface
▪ Supply voltage:
— 3.3V core and signal I/O
— 1.8V Digital control SPI I/O (3.3V-tolerant inputs)
▪ 64-VFQFPN package (9 × 9 × 0.85 mm)
▪ Ambient temperature range: -40°C to +105°C (case)