1 Features
• USB2.0 PHY transceiver chip, designed to
interface with a USB controller through a ULPI
interface, fully compliant with:
– Universal serial bus specification Rev. 2.0
– On-the-go supplement to the USB 2.0
specification Rev. 1.3
– UTMI+ low pin interface (ULPI) specification
Rev. 1.1
– ULPI 12-pin SDR interface
• DP/DM line external component compensation
(patent #US7965100 B1)
• Interfaces to host, peripheral and OTG device
cores; optimized for portable devices or system
ASICs with built-in USB OTG device core
• Complete USB OTG physical front-end that
supports host negotiation protocol (HNP) and
session request protocol (SRP)
• VBUS overvoltage protection circuitry protects VBUS
pin in range –2 V to 20 V
• Internal 5-V short-circuit protection of DP, DM, and
ID pins for cable shorting to VBUS pin
• ULPI interface:
– I/O interface (1.8 V) optimized for
nonterminated 50 Ω line impedance
– ULPI CLOCK pin (60 MHz) supports input and
output clock configurations
– Fully programmable ULPI-compliant register set
• Full industrial grade operating temperature range
from –40°C to 85°C
• Available in a 32-pin quad flat no lead [QFN
(RHB)] package

2 Applications
• Mobile phones
• Portable computers
• Tablet devices
• Video game consoles
• Desktop computers
• Portable music players

3 Description
The TUSB1210 is a USB2.0 transceiver chip,
designed to interface with a USB controller through
a ULPI interface. The device supports all USB2.0
data rates (high-speed 480 Mbps, full-speed 12 Mbps,
and low-speed 1.5 Mbps), and is compliant to both
host and peripheral modes. The device additionally
supports a UART mode and legacy ULPI serial
modes. TUSB1210 also supports the OTG (Ver1.3)
optional addendum to the USB 2.0 Specification,
including HNP and SRP.
The DP/DM external component compensation in the
transmitter compensates for variations in the series
impendence in order to match with the data line
impedance and the receiver input impedance, to limit
data reflections and thereby improve eye diagrams.