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UCD7100APWPR Folha de dados (PDF) - Texas Instruments

UCD7100APWPR Datasheet PDF - Texas Instruments
Nome de Peças UCD7100APWPR
Download  UCD7100APWPR Download
Tamanho do Arquivo   1526.76 Kbytes
página   31 Pages
Fabricante Electrônico  TI2 [Texas Instruments]
Página de início  https://www.ti.com
Logo TI2 - Texas Instruments
Descrição Electrónicos UCD7100 Digital Control Compatible Single Low-Side ±4-A MOSFET Driver with Current Sense

UCD7100APWPR Datasheet (PDF)

Go To PDF Page Download Folha de dados
UCD7100APWPR Datasheet PDF - Texas Instruments

Nome de Peças UCD7100APWPR
Download  UCD7100APWPR Click to download

Tamanho do Arquivo   1526.76 Kbytes
página   31 Pages
Fabricante Electrônico  TI2 [Texas Instruments]
Página de início  https://www.ti.com
Logo TI2 - Texas Instruments
Descrição Electrónicos UCD7100 Digital Control Compatible Single Low-Side ±4-A MOSFET Driver with Current Sense

UCD7100APWPR Folha de dados (HTML) - Texas Instruments


UCD7100APWPR Detalhes do produto

1 Features
• Adjustable current limit protection
• 3.3-V, 10-mA internal regulator
• DSP/μC compatible inputs
• Single ±4-A TrueDrive™ high current driver
• 10-ns typical rise and fall times with 2.2-nF loads
• 25-ns input-to-output propagation delay
• 25-ns current sense to output delay
• Programmable current limit threshold
• Digital output current limit flag
• 4.5-V to 15-V supply voltage range
• Rated from –40°C to 105°C
• Lead(Pb)-free packaging

2 Applications
• Digitally controlled power supplies
• DC/DC converters
• Motor controllers
• Line drivers

3 Description
The UCD7100 device is part of the UCD7K family of
digital control compatible drivers for applications that
use digital control technology that requires fast local
peak current limit protection.
The UCD7100 is a low-side ±4-A high-current
MOSFET gate driver. It allows the digital power
controllers such as UCD9110 or UCD9501 to interface
to the power stage in single ended topologies. It
provides a cycle-by-cycle current limit function with
programmable threshold and a digital output current
limit flag which can be monitored by the host
controller. With a fast 25-ns cycle-by-cycle current
limit protection, the driver can turn off the power stage
in the unlikely event that the digital system can not
respond to a failure situation in time.




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