1 Features
• Phase-locked loop based, zero-delay buffer
– 1 clock input to 2 banks of 4 outputs
– No external RC network required
• Supply voltage: 3 V to 3.6 V
• Operating frequency: 8 MHz to 200 MHz
• Low additive jitter (cycle-cycle): ±100 ps for
66 MHz to 200 MHz
• Power-down mode available
– Current consumption: < 20 μA in
Power-down mode
• 25-Ω on-chip series damping resistors
• Industrial temperature range: –40°C to 85°C
• Spread Spectrum Clock Compatible (SSC)
• Packaged in
– 9.9-mm × 3.91-mm, 16-pin SOIC (D)
– 5.0-mm × 4.4-mm, 16-pin TSSOP (PW)

2 Applications
• Defense radio
• Production switchers and mixers
• Radar
• In-vitro diagnostics
• CT & PET scanner

3 Description
The CDCVF25081 is a high performance, low skew,
low jitter, phased-locked loop clock driver. It uses a
PLL to precisely align, in both frequency and phase,
the output clocks to the input clock signal. The outputs
are divided into 2 banks for a total of 8 buffered
CLKIN outputs. The device automatically puts the
outputs to a low state when no CLKIN signal is
present (power down mode).
The S1 and S2 pins allow selection between PLL or
bypassed PLL outputs. When left open, the outputs
are disabled to a logic low state.
The part supports a fail-safe function. The device
further incorporates an input hysteresis which
prevents random oscillation of the outputs in the
absence of an input signal.
The device operates in 3.3V supply environment
and is characterized from –40°C to 85°C (ambient
temperature).