Features
• Dual CPU subsystem
- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with
• Single-cycle multiply
• Single-precision floating point unit (FPU)
• Memory protection unit (MPU)
- 100-MHz (max) 32-bit Arm® Cortex® M0+ CPU with
• Single-cycle multiply
• Memory protection unit
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0) with 92 channels
• Peripheral DMA controller #1 (P-DMA1) with 44 channels
• Memory DMA controller #0 (M-DMA0) with 4 channels

• Integrated memories
- 2112-KB of code-flash with an additional 128-KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- 256-KB of SRAM with selectable retention granularity

• Crypto engine[1]
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES[2]: 64-bit blocks, 64-bit key
- Vector unit[2] supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic
Curve (ECC)
- SHA-1/2/3[2]: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC[2]: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)