▪ Compatible with object code level with SH-
1, SH-2, and SH-3
▪ Built-in 32-bit internal data bus
▪ Supports abundant register groups
− General-purpose register: Sixteen
32-bit registers (including eight 32-
bit bank registers)
− Control register: Eight 32-bit registers
− System register: Four 32-bit registers
▪ The instruction execution time of the basic
instruction corresponds to one
instruction/cycle
▪ The logical address space corresponds to 4 GB