Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Incorporates Two Enable Inputs to Simplify
Cascading and/or Data Reception
Fully Synchronous Operation for Counting
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-μm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)

description
The 74ACT11139 is designed for use in high-performance memory-decoding or data-routing applications that
require very short propagation delay times. In high-performance memory systems, this decoder is used to
minimize the effects of system decoding.
The 74ACT11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low
enables (1G or 2G) can be used as data lines in demultiplexing applications. This decoder/demultiplexer
features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The 74ACT11139 is characterized for operation from −40°C to 85°C.