General Description

Note: Features in italics are NOT available in the 56F8145 device.

• Up to 60 MIPS at 60MHz core frequency

• DSP and MCU functionality in a unified,

C-efficient architecture

• 128KB Program Flash

• 4KB Program RAM

• 8KB Data Flash

• 8KB Data RAM

• 8KB Boot Flash

• Up to two 6-channel PWM modules

• Four 4-channel, 12-bit ADCs

• Temperature Sensor

• Up to twoQuadrature Decoders

• FlexCAN module

• Optional On-Chip Regulator

• Two Serial Communication Interfaces (SCIs)

• Up to two Serial Peripheral Interface (SPIs)

• Up to four general-purpose Quad Timers

• Computer Operating Properly (COP)/Watchdog

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 49 GPIO lines

• 128-pin LQFP Package

Features

Core

• Efficient 16-bit 56800E family controller engine with dual Harvard architecture

• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 ×16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set withunique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface

Memory

Note: Features in italics are NOT available in the 56F8145 device.

• Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security protection feature

• On-chip memory, including a low-cost, high-volume Flash solution

— 128KB of Program Flash

— 4KB of Program RAM

— 8KB of Data Flash

—8KB of Data RAM

— 8KB of Boot Flash

• EEPROM emulation capability