DESCRIPTION
The '73 is a dual flip-flop with individual
J, K, Clock and direct Reset inputs. The
7473 is positive pulse-triggered. JK infor-
mation is loaded into the master while
the Clock is HIGH and transferred to the
slave on the HIGH-to-LOW transition.
For the 7473, the J and K inputs should
be stable while the Clock is HIGH for
conventional operation.
The 74LS73 i a negative edge-triggered
flip-flop. The J and K inputs must be
stable one set-up time prior to the HIGH-
to-LOW Clock transition for predictable
operation.
The Reset (Rp) is an asynchronous
active LOW input. When LOW, it over-
rides the Clock and Data inputs, forcing
the Q output LOW and the Q output
HIGH.