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PM5377 Folha de dados (PDF) - PMC-Sierra, Inc

PM5377 Datasheet PDF - PMC-Sierra, Inc
Nome de Peças PM5377
Download  PM5377 Download
Tamanho do Arquivo   32.09 Kbytes
página   2 Pages
Fabricante Electrônico  PMC [PMC-Sierra, Inc]
Página de início  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc
Descrição Electrónicos Single Chip 96-Port STS-1/STM-0 Cross-Connect

PM5377 Datasheet (PDF)

Go To PDF Page Download Folha de dados
PM5377 Datasheet PDF - PMC-Sierra, Inc

Nome de Peças PM5377
Download  PM5377 Click to download

Tamanho do Arquivo   32.09 Kbytes
página   2 Pages
Fabricante Electrônico  PMC [PMC-Sierra, Inc]
Página de início  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc
Descrição Electrónicos Single Chip 96-Port STS-1/STM-0 Cross-Connect

PM5377 Folha de dados (HTML) - PMC-Sierra, Inc


PM5377 Detalhes do produto

FEATURES
• Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity.
• 96 ingress and 96 egress STS- 48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single device.
• Supports a single-stage, anycast switching capacity of 240G.

SWITCH PORT CONFIGURATION
• Each port can be individually configured for 2.488Gbit/s or 622Mbit/s operation. Ingress and egress links of a port can be individually configured.
• Optionally inserts AIS on ingress links that are out-of-frame.
• Supports unequipped overwrite, and path AIS overwrite on a per egress port and per egress grain basis.
• Implements the ESSI Frame layer

TOH PROCESSING AND TESTING
• Supports transport overhead processing of ports in groups of 24.
• TOH extract clock and data interface capable of extracting a set of TOH bytes per ingress port. Selection of the bytes to be extracted is user programmable on a per 24-port group basis.
• TOH insert clock and data interface capable of overwriting a set of TOH bytes per egress port. Selection of the bytes to overwrite is user programmable on a per 24-port group basis.

GLOBAL FRAME SYNCHRONIZATION
• Supports frame synchronization via a global frame pulse input signal.
• Provides software readable registers that report the difference between the arrival time of the J0 byte and the time the device frame reference expects to read the J0 byte from the ingress port FIFO on a per ingress port basis.

GENERAL
• RASIO 3G high-speed serial ingress and egress links.
• Low-power 1.2 V CMOS core logic with 2.5V digital outputs and 3.3V tolerant 2.5V digital inputs.
• 1152-pin FCBGA, 35 x 35 mm.
• Driven by a 155.52 MHz reference clock.
• Provides a standard five signal IEEE 1149.1 JTAG test port for boundary scan board test.
• Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
• 23 W typical power consumption when all features and links @ 2.488 Gbit/s are enabled and active.

APPLICATIONS
• SDH/SONET ADM
• MSPP
• Terminal Multiplexers
• Digital Cross-Connects




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