GENERAL DESCRIPTION
The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
   1.6 GHz differential clock input
   2 programmable dividers
      Divide-by in range from1 to 32
      Phase select for coarse delay adjust
   1.6 GHz LVPECL clock output
      Additive output jitter 225 fs rms
   800 MHz/250 MHz LVDS/CMOS clock output
      Additive output jitter 300 fs rms/290 fs rms
      Time delays up to 10 ns
   Device configured with 4-level logic pins
   Space-saving, 32-lead LFCSP
  
APPLICATIONS
   Low jitter, low phase noise clock distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure
   ATE