1. General description
The 74LVC1G240 is a 1-bit inverting buffer/line driver with 3-state output. The device features
an output enable OE. A HIGH on OE causes the output to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
• Wide supply voltage range from 1.65 V to 5.5 V
• High noise immunity
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8-B/JESD36 (2.7 V to 3.6 V)
• ±24 mA output drive (VCC = 3.0 V)
• ESD protection:
• • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V
• CMOS low power consumption
• Inputs accept voltages up to 5 V
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Specified from -40 °C to +85 °C and -40 °C to +125 °C