1. General description
The 74LVC2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V
or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V
environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This
device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables
the output, preventing the potentially damaging backflow current through the device when it is
powered down.
2. Features and benefits
• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• CMOS low-power dissipation
• ±24 mA output drive (VCC = 3.0 V)
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C