[Paradigm-Technology]

Description
The PDM41024 is a high-performance CMOS static RAM organized as 131,072 x 8 bits. Writing is accomplished when the write enable (WE) and the chip enable (CE1) inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE and CE2 remain HIGH and CE1 and OE are both LOW.

Features
□ High-speed access times
    Com’l: 10, 12 and 15 ns
    Ind’l: 12 and 15 ns
□ Low power operation (typical)
    - PDM41024SA
        Active: 450 mW
        Standby: 50 mW
    - PDM41024LA
       Active: 400 mW
       Standby: 25mW
□ Single +5V (±10%) power supply
□ TTL-compatible inputs and outputs
□ Packages
    Plastic SOJ (300 mil) - TSO
    Plastic SOJ (400 mil) - SO
    Plastic TSOP (I)- T