Features
• One selectable differential LVPECL output pair for DDR
533/400/667
• Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance
- One selectable core clock for the processor
- One selectable clock for the PCI/ PCI-X bus
- One 125MHz clock reference for GbE MAC
- Three 25MHz clock references for GbE PHY
• Selectable external crystal or differential (single-ended) input
source
• Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
• Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
• Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.78ps (typical), QD output
• Output supply:
LVPECL – 3.3V Core
LVCMOS –Core/Output
3.3V/3.3V
3.3V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package