HIGHLIGHTS
• The first single PLL chip:
• Features 0.5 mHz to 560 Hz bandwidth
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/
Option I) jitter generation requirements
• Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially
for Japan TCM-ISDN network timing based ADSL equipments
MAIN FEATURES
• Provides an integrated single-chip solution for Synchronous Equipment
Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4
clocks
• Employs DPLL and APLL to feature excellent jitter performance
and minimize the number of the external components
• Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine; the primary operating modes are Free-
Run, Locked and Holdover
• Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19
steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8
ppm instantaneous holdover accuracy
• Supports PBO to minimize phase transients on T0 DPLL output to
be no more than 0.61 ns
• Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports manual and automatic selected input clock switch