Features
◆ High Performance PCI Express Switch
– Three x4 ports with 12 PCI Express lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 2048 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
◆ Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin or weighted
round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
◆ Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
◆ Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC motherboards
– Supports Hot-Swap
◆ Power Management
– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Specification,
Revision 2.0 (ACPI) supporting active link state
◆ Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters