Features
This section summarizes the major features of the 106, as follows:
• 60x processor interface
— Supports up to four 60x processors
— Supports various operating frequencies and bus divider ratios
— 32-bit address bus, 64-bit data bus
— Supports full memory coherency
— Supports optional 60x local bus slave
— Decoupled address and data buses for pipelining of 60x accesses
— Store gathering on 60x-to-PCI writes
• Secondary (L2) cache control
— Configurable for write-through or write-back operation
— Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte
— Up to 4 Gbytes of cacheable space
— Direct-mapped
— Supports byte parity
— Supports partial update with external byte decode for write enables
— Programmable interface timing
— Supports pipelined burst, synchronous burst, or asynchronous SRAMs
— Alternately supports an external L2 cache controller or integrated L2 cache module
• Memory interface
— 1 Gbyte of RAM space, 16 Mbytes of ROM space
— Supports parity or error checking and correction (ECC)
— High-bandwidth, 64-bit data bus (72 bits including parity or ECC)
— Supports fast page mode DRAMs, extended data out (EDO) DRAMs, and synchronous
DRAMs (SDRAMs)
— Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 2 Mbyte to
128 Mbytes per bank
— ROM space may be split between the PCI bus and the 60x/memory bus (8 Mbytes each)
— Supports 8-bit asynchronous ROM or 64-bit burst-mode ROM
— Supports writing to Flash ROM
— Configurable external buffer control logic
— Programmable interface timing
• PCI interface
— Compliant with
PCI Local Bus Specification,
Revision 2.1
— Supports PCI interlocked accesses to memory using LOCK signal and protocol
— Supports accesses to all PCI address spaces
— Selectable big- or little-endian operation
— Store gathering on PCI writes to memory
— Selectable memory prefetching of PCI read accesses
— Only one external load presented by the MPC106 to the PCI bus
— Interface operates at 20–33 MHz
— Word parity supported
— 3.3 V/5.0 V-compatible
• Support for concurrent transactions on 60x and PCI buses
• Power management
— Fully-static 3.3-V CMOS design
— Supports 60x nap, doze, and sleep power management modes and suspend mode
• IEEE 1149.1-compliant, JTAG boundary-scan interface
• 304-pin ceramic ball grid array (CBGA) package