Features
This section describes details of the 602 implementation of the PowerPC architecture. Major features of the
602 are as follows:
• High-performance, superscalar microprocessor
— As many as two instructions are fetched from the instruction queue per clock
— One instruction can be issued and one retired per clock
— As many as four instructions in execution per clock
— Single-cycle execution for most instructions
• Four independent execution units and two register files
— BPU performs architecturally-defined static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for single-precision operations
— Emulation support for double-precision operations
— An implementation of the non-IEEE floating-point mode
— Thirty-two 32-bit general-purpose registers (GPRs) for integer operands
— Thirty-two 32-bit floating-point registers (FPRs) for single-precision operands
— LSU for data transfer between data cache and GPRs and FPRs
• Instruction pipelining and split cache organization
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— BPU that performs CR lookahead operations
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
(one of which is a branch instruction)
— A four-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 4-Kbyte data cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— 4-Kbyte instruction cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
• Memory managament features
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 32-entry, two-way set-associative ITLB
— A 32-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
— Optional configuration of the TLBs that offers protection for up to 4-Mbytes of memory per
TLB, but no effective address translation
• Facilities for enhanced system performance
— A 64-bit (address and data multiplexed) external data bus with burst transfers
— Support for injected snoops by other devices during ownership of bus tenure
— Ability to broadcast a line-fill address, during the address tenure of a writeback transaction on
the bus
• Integrated power management
— Low-power 3.3-volt design
— Internal processor/bus clock multiplier that provides 2/1 and 3/1 ratios
— Three static power-saving modes—doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• Data bus externally selectable as either 32 or 64 bits
• In-system testability and debugging features through JTAG port
• Three power saving modes
— Doze—All the functional units of the 602 are disabled except for the time base/decrementer
registers and the bus snooping logic. When the processor is in doze mode, an external
asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft
reset, or machine check brings the 602 into the full-power state. The 602 in doze mode
maintains the PLL in a fully-powered state and locked to the system external clock input
(SYSCLK) so a transition to the full-power state takes only a few processor clock cycles.
— Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving
only the time base register and the PLL in a powered state. The 602 returns to the full-power
state upon receipt of an external asynchronous interrupt, a system management interrupt, a
decrementer exception, a hard or soft reset, or a machine check input (MCP). A return to fullpower
state from a nap state takes only a few processor clock cycles.
— Sleep—Sleep mode reduces power consumption to a minimum by disabling all internal
functional units, after which external system logic may disable the PLL and SYSCLK.
Returning the 602 to the full-power state requires the enabling of the PLL and SYSCLK,
followed by the assertion of an external asynchronous interrupt, a system management
interrupt, a hard or soft reset, or a machine check input (MCP) signal after the time required to
relock the PLL