Features
This section summarizes features of the MPC750’s implementation of the PowerPC architecture. Major
features of the MPC750 are as follows:
• Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving 2 speculations)
— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch
delay slots
• Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit
1, fixed-point unit 2, or floating-point)
— Serialization control (predispatch, postdispatch, execution serialization)
• Decode
— Register file access
— Forwarding control
— Partial instruction decode
• Load/store unit
— One cycle load or store cache access (byte, half-word, word, double-word)
— Effective address generation
— Hits under misses (one outstanding miss)
— Single-cycle misaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian support in hardware
• Fixed-point units
— Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shift, rotate, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
• Floating-point unit
— Support for IEEE-754 standard single- and double-precision floating-point arithmetic
— 3 cycle latency, 1 cycle throughput, single-precision multiply-add
— 3 cycle latency, 1 cycle throughput, double-precision add
— 4 cycle latency, 2 cycle throughput, double-precision multiply-add
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
• System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
• Cache structure
— 32K, 32-byte line, 8-way set associative instruction cache
— 32K, 32-byte line, 8-way set associative data cache
— Single-cycle cache access
— Pseudo-LRU replacement
— Copy-back or write-through data cache (on a page per page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking instruction and data cache (one outstanding miss under hits)
— No snooping of instruction cache
• Memory management unit
— 128 entry, 2-way set associative instruction TLB
— 128 entry, 2-way set associative data TLB
— Hardware reload for TLBs
— 4 instruction BATs and 4 data BATs
— Virtual memory support for up to 4 exabytes (252) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
• Level 2 (L2) cache interface (not implemented on MPC740)
— Internal L2 cache controller and 4K-entry tags; external data SRAMs
— 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size
— Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous
burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
• Bus interface
— Compatible with 60x processor interface
— 32-bit address bus
— 64-bit data bus
— Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x
supported
• Integrated power management
— Low-power 2.6/3.3-volt design
— Three static power saving modes: doze, nap, and sleep
• Integrated Thermal Management Assist Unit
— On-chip thermal sensor and control logic
— Thermal Management Interrupt for software regulation of junction temperature.
• Testability
— LSSD scan design
— JTAG interface
• Reliability and serviceability—Parity checking on 60x and L2 cache buses