Features
• One differential HSTL output pair
One differential feedback output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential 
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 630MHz
• Input frequency range: 31.25MHz to 630MHz
•VCO range: 250MHz to 630MHz
• External feedback for “zero delay” clock regeneration 
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 50ps (maximum)
• Output skew: 50ps (maximum)
• Static phase offset: 200ps (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature