DESCRIPTION:
The CSPT857C is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential output
pairs (Y [0:9],Y [0:9]) and one differential pair of feedback clock output (FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the input frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption of less than 200μA.
The CSPT857C requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857C,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857C is available in Commercial Temperature Range (0°C to
+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering
Information for details.

FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 220MHz
• Very low skew:
– <100ps for PC1600 - PC2700
– <75ps for PC3200
• Very low jitter:
– <75ps for PC1600 - PC2700
– <50ps for PC3200
• 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700
• 2.6V AVDD and 2.6V VDDQ for PC3200
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP, 40-pin VFQFPN, and 56-pin VFBGA
packages