Features
• AEC-Q10x qualified
• Core
– Max fCPU: 16 MHz
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Average 1.6 cycles/instruction resulting in
10 MIPS at 16 MHz fCPU for industry
standard benchmark
• Memories
– Flash Program memory: 16 to 32 Kbyte
Flash; data retention 20 years at 55 °C
after 1 kcycle
– Data memory: 0.5 to 1 Kbyte true data
EEPROM; endurance 300 kcycle
– RAM: 2 Kbyte
• Clock management
– Low-power crystal resonator oscillator with
external clock input
– Internal, user-trimmable 16 MHz RC and
low-power 128 kHz RC oscillators
– Clock security system with clock monitor
• Reset and supply management
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating
– Low consumption power-on and powerdown
reset
• Interrupt management
– Nested interrupt controller with 32 vectors
– Up to 34 external interrupts on 5 vectors
• Timers
– Up to 2 general purpose 16-bit PWM timers
with up to 3 CAPCOM channels each (IC,
OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, deadtime
insertion and flexible synchronization
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
– Window and independent watchdog timers
• Communication interfaces
– LINUART
– LIN 2.2 compliant, master/slave modes
with automatic resynchronization
– SPI interface up to 8 Mbit/s or fMASTER/2
– I2C interface up to 400 Kbit/s
• Analog-to-digital converter (ADC)
– 10-bit accuracy, 2LSB TUE accuracy, 2LSB
TUE linearity ADC and up to 10 multiplexed
channels with individual data buffer
– Analog watchdog, scan and continuous
sampling mode
• I/Os
– Up to 38 user pins including 10 HS I/Os
– Highly robust I/O design, immune against
current injection
• Operating temperature up to 150 °C
• Qualification conforms to AEC-Q100 rev G