Description
The 8SLVD1204 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1204 is
characterized to operate from a 2.5V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1204 ideal for those clock distribution applications demanding
well-defined performance and repeatability.
Two selectable differential inputs and four low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.

Features
• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 300ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
10kHz - 20MHz: 95fs (maximum)
• Full 2.5V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFPN packaging
• Supports case temperature ≤ 105°C operations
• -40°C to 85°C ambient operating temperature