Features

• Organization: 131,072 words × 32 or 36 bits

• Fast clock speeds to 200 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns

• Fully synchronous register-to-register operation

• Single register “Flow-through” mode

• Single-cycle deselect

• Dual-cycle deselect also available (AS7C33128PFD32A/AS7C33128PFD36A)

• Pentium®1 compatible architecture and timing

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3 core power supply

• 2.5V or 3.3V I/O operation with separate VDDQ

• 30 mW typical standby power in power down mode

• NTD™1 pipeline architecture available

   (AS7C33128NTD32A/ AS7C33128NTD36A)