 |
Os motores de busca de Datasheet de Componentes eletrônicos |
|
|
Os motores de busca de Datasheet de Componentes eletrônicos |
|
R5F564MLDDFC Folha de dados(PDF) 179 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F564MLDDFC Folha de dados(HTML) 179 Page - Renesas Technology Corp |
|
|
179 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 179 of 228 Oct 24, 2016 RX64M Group 5. Electrical Characteristics Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1 Note 3. When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1 Table 5.32 SCI and SCIF Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF High-drive output is selected by the driving ability control register. Item Symbol Min.*1 Max.*1 Unit*1 Test Conditions SCI Input clock cycle Asynchronous tScyc 4 — tPBcyc Figure 5.44 Clock synchronous 6— Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*2 tScyc 8— tPBcyc Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Clock synchronous tTXD — 28 ns Figure 5.45 Receive data setup time Clock synchronous tRXS 15 — ns Receive data hold time Clock synchronous tRXH 5— ns SCIF Input clock cycle Asynchronous tScyc 4— tPAcyc Figure 5.44 Clock synchronous 12 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*3 tScyc 8— tPAcyc Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Master tTXD — 10 ns Figure 5.45 Slave — 4 × tPAcyc + 20 Receive data setup time Master tRXS 3 × tPAcyc + 20 — ns Slave tPAcyc + 10 — Receive data hold time Master tRXH -3 × tPAcyc + 5 — ns Slave 2 × tPAcyc + 10 — |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
