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R5F564MLDDFC Folha de dados(PDF) 148 Page - Renesas Technology Corp

Nome de Peças R5F564MLDDFC
Descrição Electrónicos  120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory
PDF  228 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F564MLDDFC Folha de dados(HTML) 148 Page - Renesas Technology Corp

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R01DS0173EJ0110 Rev.1.10
Page 148 of 228
Oct 24, 2016
RX64M Group
5. Electrical Characteristics
5.3.2
Clock Timing
Figure 5.3
BCLK Pin and SDCLK Pin Output Timing
Table 5.11
BCLK Pin Output, SDCLK Pin Output Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
BCLK pin output cycle time
Packages with 177 to
144 pins
tBcyc
16.6
—
—
ns
Figure 5.3
Packages with 100
pins or less
33.2
—
—
ns
BCLK pin output high pulse width
tCH
3.3
—
—
ns
BCLK pin output low pulse width
tCL
3.3
—
—
ns
BCLK pin output rising time
tCr
——
5
ns
BCLK pin output falling time
tCf
——
5
ns
SDCLK pin output cycle time
Packages with 177 to
144 pins
tBcyc
16.6
—
—
ns
SDCLK pin output high pulse width
tCH
3.3
—
—
ns
SDCLK pin output low pulse width
tCL
3.3
—
—
ns
SDCLK pin output rising time
tCr
——
5
ns
SDCLK pin output falling time
tCf
——
5
ns
tCf
tCH
tBcyc, tSDcyc
tCr
tCL
BCLK pin output, SDCLK pin output
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, C = 30 pF



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