5V41236PGGI8 datasheet(10/18 Pages) IDT

Nome de Peças	5V41236PGGI8

Descrição Electrónicos	4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

PDF	18 Pages

Scroll/Zoom	100%

Fabricante Electrônico	IDT [Integrated Device Technology]

Página de início	http://www.idt.com

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10 / 18 page

IDT5V41236

4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

10

IDT5V41236

APRIL 4, 2017

AC Electrical Characteristics - CLKOUT (A:D)

Unless stated otherwise, VDD=3.3V ±5%, Ambient Temperature -40 to +85

C

1 Test setup is R

S=33RP=50 with CL=2 pF, Rr = 475 (1%).

2 Measurement taken from a single-ended waveform.

3 Measurement taken from a differential waveform.

4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.

5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its

PD = low.

Electrical Characteristics - Differential Phase Jitter

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

25

MHz

Output Frequency

HCSL termination

25

200

MHz

Output Max. Voltage1,2

VMAX

660

863

1150

mV

Output Min. Voltage1,2

VMIN

-300

-53

mV

Crossing Point Voltage1,2

Absolute

250

377

550

mV

Crossing Point Voltage1,2,4

Variation over all edges

45

140

mV

Jitter, Cycle-to-Cycle1,3

29

125

ps

Modulation Frequency

Spread spectrum

30

32.9

33

kHz

Rise Time1,2

tOR

From 0.175V to 0.525V

175

237

700

ps

Fall Time1,2

tOF

From 0.525V to 0.175V

175

286

700

ps

Rise/Fall Time Variation1,2

73

125

ps

Skew between Outputs

8

50

ps

Duty Cycle1,3

45

52

55

%

Output Enable Time5

All outputs

100

ns

Output Disable Time5

All outputs

100

ns

Stabilization Time

tSTABLE

From power-up VDD=3.3V

1

1.8

ms

Spread Change Time

tSPREAD

Settling period after spread change

30

ms

PARAMETER

Symbol

Conditions

Min

Typ

Max

Units

Notes

tjphaseG1

PCIe Gen 1

30

86

ps (p-p) 1,2,3

tjphaseG2Lo

PCIe Gen 2

10kHz < f < 1.5MHz

13

ps

(RMS)

1,2,3

tjphaseG2High

PCIe Gen 2

1.5MHz < f < Nyquist (50MHz)

2.3

3.1

ps

(RMS)

1,2,3

tjphaseG3

PCIe Gen 3

0.7

1

ps

(RMS)

1,2,3

1Guaranteed by design and characterization, not 100% tested in production.

TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%

2See http://www.pcisig.com for complete specs

3Applies to 100MHz, spread off and 0.5% down spread only.

SPEC

Jitter, Phase

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