ST7LITE49K2 datasheet(116/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

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Counter register (CR)

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Counter high register (CHR) is the most significant byte (MSB).

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Counter low register (CLR) is the least significant byte (LSB).

Alternate counter register (ACR)

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Alternate counter high register (ACHR) is the MSB.

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Alternate counter low register (ACLR) is the LSB.

These two read-only 16-bit registers contain the same value but with the difference that

reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the

status register, (SR), (see16-bit read sequence (from either the counter register or the

alternate counter register) on page 118).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh

value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in

the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and

PWM mode.

The timer clock depends on the clock control bits of the CR2 register, as illustrated in

Table 37. The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU

clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4,

fCPU/8 or an external frequency.

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