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TNETV6446AINZWT Folha de dados(PDF) 131 Page - Texas Instruments |
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TNETV6446AINZWT Folha de dados(HTML) 131 Page - Texas Instruments |
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131 / 227 page  TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 6.10 External Memory Interface (EMIF) DM6446 supports several memory and external device interfaces, including: • Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc. • NAND Flash • ATA/CF 6.10.1 Asynchronous EMIF (EMIFA) The DM6446 Asynchronous EMIF (EMIFA) provides an 8-bit or 16-bit data bus, an address bus width up to 24-bits, and 4 dedicated chip selects, along with memory control signals. These signals are multiplexed between three peripherals: • EMIFA and NAND interfaces • ATA/CF • Host Port Interface 6.10.1.1 NAND (NAND, SmartMedia, xD) The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided and each are individually configurable to provide either EMIFA or NAND support. The NAND features supported are as follows. • NAND flash on up to 4 asynchronous chip selects. • 8 and 16-bit data bus widths. • Programmable cycle timings. • Performs ECC calculation. • NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory cards • ARM ROM supports booting of the DM6446 ARM processor from NAND flash located at CS2 The memory map for EMIFA and NAND registers is shown in Table 6-33. For more details on the EMIFA and NAND interfaces, see the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19) and the TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) Reference Guide (literature number SPRUE20). Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 131 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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