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TNETV6446AINZWT Folha de dados(PDF) 167 Page - Texas Instruments

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Nome de Peças TNETV6446AINZWT
Descrição Electrónicos  Digital Media System-on-Chip
PDF  227 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV6446AINZWT Folha de dados(HTML) 167 Page - Texas Instruments

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PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
7, 9
HD/VD
CCD[15:0]
8, 10
11, 13
12, 14
5
6
C_WE/C_FIELD
PCLK
(Positive Edge Clocking)
15
16
23
24
CCD[15:0]
C_WE
PCLK
(Negative Edge Clocking)
TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Figure 6-47. VPFE (CCD) Slave Mode Input Data Timing
Table 6-55. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 6-48)
A-513,
-594,
NO.
UNIT
-810
MIN
MAX
15
tsu(CCDV-PCLK)
Setup time, CCD valid before PCLK edge
3
ns
16
th(PCLK-CCDV)
Hold time, CCD valid after PCLK edge
2
ns
23
tsu(CWEV-PCLK)
Setup time, C_WE valid before PCLK edge
3
ns
24
th(PCLK-CWEV)
Hold time, C_WE valid after PCLK edge
2
ns
(1)
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
Figure 6-48. VPFE (CCD) Master Mode Input Data Timing
Copyright © 2005–2010, Texas Instruments Incorporated
Peripheral and Electrical Specifications
167
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Product Folder Link(s): TMS320DM6446



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