STM32F479II datasheet(182/208 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F479xx

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DocID028010 Rev 2

Figure 72. Quad-SPI DDR timing diagram

5.3.31

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 109 for DCMI are derived

from tests performed under the ambient temperature, fHCLK frequency and VDD supply

voltage summarized in Table 17, with the following configuration:

•

DCMI_PIXCLK polarity: falling

•

DCMI_VSYNC and DCMI_HSYNC polarity: high

•

Data formats: 14 bits

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5 VDD

Table 108. Quad-SPI characteristics in DDR mode(1)

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Fck

1/t(CK)

Quad-SPI clock frequency

2.7 V ≤ VDD ≤ 3.6 V,

CL = 20 pF

MHz

1.71 V ≤ VDD ≤ 3.6 V,

CL = 15 pF

tw(CKH)

Quad-SPI clock high time

‐

t(CK)/2-1

t(CK)/2

tw(CKL)

Quad-SPI clock low time

t(CK)/2

t(CK)/2+1

tsr(IN)

tsf(IN)

Data input set-up time

2.7 V ≤ VDD ≤ 3.6 V

1.71 V ≤ VDD ≤ 3.6 V

0.5

thr(IN)

thf(IN)

Data input hold time

2.7 V ≤ VDD ≤ 3.6 V

1.71 V ≤ VDD ≤ 3.6 V

4.5

tvr(OUT)

tvf(OUT)

Data output valid time

DHHC=0

10.5

DHHC=1

Pres=1,2…

-Thclk/2+2 Thclk/2+2.5

th(OUT)

tf(OUT)

Data output hold time

DHHC=0

DHHC=1

Pres=1,2…

Thclk/2+0.5

1. Guaranteed based on test during characterization.

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