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STM32F756VG Folha de dados(PDF) 192 Page - STMicroelectronics |
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STM32F756VG Folha de dados(HTML) 192 Page - STMicroelectronics |
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192 / 228 page ![]() Electrical characteristics STM32F756xx 192/228 DocID027589 Rev 4 Figure 72. Quad-SPI timing diagram - SDR mode Figure 73. Quad-SPI timing diagram - DDR mode 5.3.29 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 108 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits Table 108. DCMI characteristics(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK -0.4 DCMI_PIXCLK Pixel clock input - 54 MHz DPixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 3.5 - ns th(DATA) Data input hold time 0 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 2.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 0 - |
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