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9DMU0431 Folha de dados(PDF) 5 Page - Integrated Device Technology

Nome de Peças 9DMU0431
Descrição Electrónicos  HCSL differential inputs
PDF  11 Pages
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Fabricante Electrônico  IDT [Integrated Device Technology]
Página de início  http://www.idt.com
Logo IDT - Integrated Device Technology

9DMU0431 Folha de dados(HTML) 5 Page - Integrated Device Technology

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REVISION A 09/24/14
5
2:4 1.5V PCIE GEN1-2-3 CLOCK MUX
9DMU0431 DATASHEET
Electrical Characteristics–Absolute Maximum Ratings
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Supply Voltage
VDDx
-0.5
2
V
1,2
Input Voltage
VIN
-0.5
VDD+0.5
V
1,3
Input High Voltage, SMBus
VIHSMB
SMBus clock and data pins
3.3
V
1
Storage Temperature
Ts
-65
150
°C
1
Junction Temperature
Tj
125
°C
1
Input ESD protection
ESD prot
Human Body Model
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.0V.
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
1.425
1.5
1.575
V
Ambient Operating
Temperature
TAMB
Industrial range
-40
25
85
°C
1
Input High Voltage
VIH
Single-ended inputs, except SMBus
0.75 VDD
VDD + 0.3
V
Input Low Voltage
VIL
Single-ended inputs, except SMBus
-0.3
0.25 VDD
V
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
Input Frequency
Fin
1
167
MHz
2
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs, except DIF_IN
1.5
5
pF
1
CINDIF_IN
DIF_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms
1,2
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30
33
kHz
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
066
kHz
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
3
clocks
1,3
Tfall
tF
Fall time of single-ended control inputs
5
ns
2
Trise
tR
Rise time of single-ended control inputs
5
ns
2
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 DIF_IN input
Capacitance
Input Current


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