AT90PWM2 datasheet(124/365 Pages) ATMEL

124 / 365 page

124

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

Figure 15-12. Timer/Counter Timing Diagram, no Prescaling

Figure 15-13 shows the same timing data, but with the prescaler enabled.

Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

15.10 16-bit Timer/Counter Register Description

15.10.1

Timer/Counter1 Control Register A – TCCR1A

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B

The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-

tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOP

TOP - 1

TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

(clk

I/O/1)

clk

I/O

TOVn(FPWM)

and ICF n(if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOP

TOP - 1

TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

3210

COM1A1

COM1A0

COM1B1

COM1B0

–

WGM11

WGM10

TCCR1A

Read/Write

R/W

Initial Value

0000

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