PIC16C71 datasheet(129/337 Pages) MICROCHIP

129 / 337 page

DS30234D-page 129

PIC16C6X

13.4

Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator Start-up

Timer (OST) and Brown-out Reset

(BOR)

13.4.1

POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR/VPP pin

directly (or through a resistor) to VDD. This will elimi-

nate external RC components usually needed to create

a Power-on Reset. A maximum rise time for VDD is

required. See Electrical Speciﬁcations for details.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, ...) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met. Brown-out Reset may be used to meet the startup

conditions.

For additional information, refer to Application Note

AN607, “

Power-up Trouble Shooting.”

13.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms nominal

time-out on power-up only, from POR. The Power-up

Timer operates on an internal RC oscillator. The chip is

kept in reset as long as PWRT is active. The PWRT’s

time delay allows VDD to rise to an acceptable level. A

conﬁguration bit is provided to enable/disable the

PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

13.4.3

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures the crystal oscillator

or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

13.4.4

BROWN-OUT RESET (BOR)

A conﬁguration bit, BODEN, can disable (if clear/pro-

grammed) or enable (if set) the Brown-out Reset cir-

cuitry. If VDD falls below 4.0V (parameter D005 in

Electrical Speciﬁcation section) for greater than param-

eter #34 (see Electrical Speciﬁcation section), the

brown-out situation will reset the chip. A reset may not

occur if VDD falls below 4.0V for less than parameter

#34. The chip will remain in Brown-out Reset until VDD

rises above BVDD. The Power-up Timer will now be

invoked and will keep the chip in RESET an additional

72 ms. If VDD drops below BVDD while the Power-up

Timer is running, the chip will go back into a Brown-out

Reset and the Power-up Timer will be initialized. Once

VDD rises above BVDD, the Power-up Timer will exe-

cute a 72 ms time delay. The Power-up Timer should

always be enabled when Brown-out Reset is enabled.

Figure 13-10 shows typical brown-out situations.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 13-10: BROWN-OUT SITUATIONS

72 ms

BVDD Max.

BVDD Min.

VDD

Internal

Reset

BVDD Max.

BVDD Min.

VDD

Internal

Reset

72 ms

<72 ms

72 ms

BVDD Max.

BVDD Min.

VDD

Internal

Reset

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