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STM32F205RB Folha de dados(PDF) 105 Page - STMicroelectronics

Nome de Peças STM32F205RB
Descrição Electrónicos  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  163 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F205RB Folha de dados(HTML) 105 Page - STMicroelectronics

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STM32F205xx, STM32F207xx
Electrical characteristics
Doc ID 15818 Rev 7
105/163
Figure 44.
USB OTG FS timings: definition of data signal rise and fall time
USB HS characteristics
Table 54 shows the USB HS operating voltage.
Table 53.
USB OTG FS electrical characteristics(1)
1.
Guaranteed by design, not tested in production.
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
2.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF
420
ns
tf
Fall time(2)
CL = 50 pF
4
20
ns
trfm
Rise/ fall time matching
tr/tf
90
110
%
VCRS
Output signal crossover voltage
1.3
2.0
V
Table 54.
USB HS DC electrical characteristics
Symbol
Parameter
Min.(1)
1.
All the voltages are measured from the local ground potential.
Max.(1)
Unit
Input level
VDD
Ethernet operating voltage
2.7
3.6
V
Table 55.
Clock timing parameters
Parameter(1)
1.
Guaranteed by design, not tested in production.
Symbol
Min
Nominal
Max
Unit
Frequency (first transition)
8-bit ±10%
FSTART_8BIT
54
60
66
MHz
Frequency (steady state) ±500 ppm
FSTEADY
59.97
60
60.03
MHz
Duty cycle (first transition)
8-bit ±10%
DSTART_8BIT
40
50
60
%
Duty cycle (steady state) ±500 ppm
DSTEADY
49.975
50
50.025
%
Time to reach the steady state frequency and
duty cycle after the first transition
TSTEADY
--
1.4
ms
Clock startup time after the
de-assertion of SuspendM
Peripheral
TSTART_DEV
--
5.6
ms
Host
TSTART_HOST
--
-
PHY preparation time after the first transition
of the input clock
TPREP
--
-
µs
ai14137
tf
Differen tial
data lines
VSS
VCRS
tr
Crossover
points



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