AM8530 datasheet(145/194 Pages) AMD

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AMD

6–35

Table 6–10. Residue Bits/Character

Residue

Bits/Char

801

700

601

500

Bit 0: All Sent

In Asynchronous mode, this bit is set when all characters have completely cleared the

transmitter. Most modems contain additional delays in the data path, which require the

modem control signals remain active until after the data have cleared both the transmitter

and the modem. This bit is always set in synchronous and SDLC modes.

6.3.3

Read Register 2

RR2 contains the interrupt vector written into WR2. When the register is accessed in

Channel A, the vector returned is the vector actually stored in WR2. When this register is

accessed in Channel B, the vector returned includes status information in bits 1, 2, and 3

or in bits 6, 5, and 4, depending on the state of the Status High/Status Low bit in WR9

and independent of the state of VIS bit in WR9. The vector is modified according to Table

6–4 shown in the explanation of the VIS bit in WR9. If no interrupts are pending, the

status is V3, V2, V1 = 011, or V6, V5, V4 = 110. Only one vector register exists in the

SCC, but it can be accessed through either channel. Figure 6–20 shows the bit positions

for RR2.

D7 D6 D5 D4 D3 D2 D1 D0

Interrupt Vector*

*Modified in B Channel

Figure 6–20. Read Register 2

6.3.4

Read Register 3

RR3 is the Interrupt Pending register. The status of each of the Interrupt Pending bits in

the SCC is reported in this register. This register exists only in Channel A. If this register

is accessed in Channel B, all ‘0’s are returned. The two unused bits are always returned

as ‘0’. Figure 6–21 shows the bit positions for RR3.

AM8530 Folha de dados(PDF) 145 Page - Advanced Micro Devices