PIC18F4680ISPSQTP datasheet(408/482 Pages) MICROCHIP

408 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 406

Preliminary

MOVSS

Move Indexed to Indexed

Syntax:

MOVSS [zs], [zd]

Operands:

≤ zs ≤ 127

≤ zd ≤ 127

Operation:

((FSR2) + zs) → ((FSR2) + zd)

Status Affected:

None

Encoding:

1st word (source)

2nd word (dest.)

1110

1111

1011

xxxx

1zzz

xzzz

zzzzs

zzzzd

Description

The contents of the source register are

moved to the destination register. The

addresses of the source and destination

registers are determined by adding the

7-bit literal offsets ‘zs’ or ‘zd’,

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

The MOVSS instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Words:

Cycles:

Q Cycle Activity:

Decode

Determine

source addr

Determine

source addr

Read

source reg

Decode

Determine

dest addr

Determine

dest addr

Write

to dest reg

Example:

MOVSS

[05h], [06h]

Before Instruction

FSR2

80h

Contents

of 85h

33h

Contents

of 86h

11h

After Instruction

FSR2

80h

Contents

of 85h

33h

Contents

of 86h

33h

PUSHL

Store Literal at FSR2, Decrement FSR2

Syntax:

PUSHL k

Operands:

≤ k ≤ 255

Operation:

→ (FSR2),

FSR2 – 1

→ FSR2

Status Affected: None

Encoding:

1111

1010

kkkk

Description:

The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2 is

decremented by 1 after the operation.

This instruction allows users to push values

onto a software stack.

Words:

Cycles:

Q Cycle Activity:

Decode

Read ‘k’

Process

data

Write to

destination

Example:

PUSHL

08h

Before Instruction

FSR2H:FSR2L

01ECh

Memory (01ECh)

00h

After Instruction

FSR2H:FSR2L

01EBh

Memory (01ECh)

08h

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