PIC18F2680ISPSQTP datasheet(398/482 Pages) MICROCHIP

398 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 396

Preliminary

SLEEP

Enter Sleep mode

Syntax:

SLEEP

Operands:

None

Operation:

00h

→ WDT,

→ WDT postscaler,

→ TO,

→ PD

Status Affected:

TO, PD

Encoding:

0000

0011

Description:

The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. Watchdog Timer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Process

Data

Go to

Sleep

Example:

SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake-up, this bit is cleared.

SUBFWB

Subtract f from W with Borrow

Syntax:

SUBFWB

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W) – (f) – (C)

→ dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0101

01da

ffff

Description:

Subtract register ‘f’ and Carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example 1:

SUBFWB

REG, 1, 0

Before Instruction

REG

After Instruction

REG

; result is negative

Example 2:

SUBFWB

REG, 0, 0

Before Instruction

REG

After Instruction

REG

; result is positive

Example 3:

SUBFWB

REG, 1, 0

Before Instruction

REG

After Instruction

REG

; result is zero

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