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DM3725CBC Folha de dados(PDF) 146 Page - Texas Instruments

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Nome de Peças DM3725CBC
Descrição Electrónicos  Digital Media Processors
PDF  280 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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DM3725CBC Folha de dados(HTML) 146 Page - Texas Instruments

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DM3730, DM3725
SPRS685D
– AUGUST 2010 – REVISED JULY 2011
www.ti.com
Table 4-24. Graphic Accelerator Clocks(2)
OPP 100(2)
Max Freq
Max Freq
Max Freq
Description
Source Clock
Ratio
Ratio
Ratio
(MHz)
(MHz)
(MHz)
DPLL3 Locked Frequency
800
664
532
DPLL4 Locked Frequency
1728
1728
1728
1 * (M2 =
1 * (M2 =
1 * (M2 =
DPLL3CLKOUTX2_M2
DPLL3 Locked Frequency
800
664
532
1)(1)(3)
1)(1)(3)
1)(1)(3)
2 * (M2 =
2 * (M2 =
2 * (M2 =
DPLL3CLKOUT_M2
DPLL3 Locked Frequency
400
332
266
1)(1)(3)
1)(1)(3)
1)(1)(3)
1 * (M2 =
1 * (M2 =
1 * (M2 =
DPLL4CLKOUT_M2
DPLL4 Locked Frequency
192
192
192
9)(1)(3)
9)(1)(3)
9)(1)(3)
CORE_CLK
DPLL4 Locked Frequency
400
1
332
1
266
1
COREX2_CLK
DPLL3CLKOUTX2_M2
800
1
664
1
532
1
SGX_192M_FCLK
DPLL4CLKOUT_M2
192
1
192
1
192
1
SGX
– Option 1
CORE_CLK
200
2
166
2
133
2
SGX
– Option 2
COREX2_CLK
177.3
3
SGX
– Option 3
SGX_192M_FCLK
192
1
192
1
192
1
(1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference
Manual (SPRUGN4).
(2) SGX (Graphic Accelerator) is not available in OPP50 operating point.
(3) The DPLL ratios documented in this table are recommended ratios. Other values may apply.
146
Clock Specifications
Copyright
© 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): DM3730 DM3725



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